US 11,943,939 B2
Integrated circuit device and method
Meng-Kai Hsu, Hsinchu (TW); Jerry Chang Jui Kao, Hsinchu (TW); Chin-Shen Lin, Hsinchu (TW); Ming-Tao Yu, Hsinchu (TW); Tzu-Ying Lin, Hsinchu (TW); and Chung-Hsing Wang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jan. 4, 2021, as Appl. No. 17/140,441.
Prior Publication US 2022/0216270 A1, Jul. 7, 2022
Int. Cl. H10K 19/10 (2023.01); H01L 21/822 (2006.01); H01L 27/06 (2006.01); H01L 49/02 (2006.01); H10K 19/00 (2023.01)
CPC H10K 19/10 (2023.02) [H01L 21/822 (2013.01); H01L 27/0688 (2013.01); H01L 28/10 (2013.01); H01L 28/40 (2013.01); H10K 19/201 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device, comprising:
a substrate; and
a circuit region over the substrate, the circuit region comprising:
at least one active region extending along a first direction;
at least one gate region extending across the at least one active region and along a second direction transverse to the first direction; and
at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region,
wherein
the at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction,
the circuit region has a boundary, and
the at least one first IO pattern is completely arranged within the boundary of the circuit region.