US 11,943,933 B2
Ferroelectric memory device using back-end-of-line (BEOL) thin film access transistors and methods for forming the same
Bo-Feng Young, Taipei (TW); Mauricio Manfrini, Zhubei (TW); Sai-Hooi Yeong, Zhubei (TW); Han-Jong Chia, Hsinchu (TW); and Yu-Ming Lin, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Jan. 17, 2023, as Appl. No. 18/098,093.
Application 18/098,093 is a continuation of application No. 17/230,598, filed on Apr. 14, 2021, granted, now 11,569,250.
Claims priority of provisional application 63/045,385, filed on Jun. 29, 2020.
Prior Publication US 2023/0157031 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 53/30 (2023.01); G11C 11/22 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H10B 53/30 (2023.02) [G11C 11/221 (2013.01); G11C 11/2259 (2013.01); G11C 11/2275 (2013.01); H01L 21/02565 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
metal interconnect structures embedded within dielectric material layers that overlie a top surface of a substrate;
a thin film transistor embedded in a first dielectric material layer selected from the dielectric material layers, and is vertically spaced from the top surface of the substrate; and
a ferroelectric memory cell embedded within the dielectric material layers,
wherein a first node of the ferroelectric memory cell is electrically connected to a node of the thin film transistor through a subset of the metal interconnect structures that is located above, and vertically spaced from, the top surface of the substrate, wherein the ferroelectric memory cell is located at a same level as the thin film transistor and is laterally surrounded by the first dielectric material layer.