US 11,943,931 B2
Non-volatile memory device with vertical state transistor and vertical selection transistor
Quentin Hubert, Marseilles (FR); Abderrezak Marzaki, Aix en Provence (FR); and Julien Delalleau, Marseilles (FR)
Assigned to STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed by STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed on Apr. 1, 2021, as Appl. No. 17/220,286.
Application 17/220,286 is a division of application No. 16/391,768, filed on Apr. 23, 2019, granted, now 10,991,710.
Claims priority of application No. 1853887 (FR), filed on May 4, 2018.
Prior Publication US 2021/0225853 A1, Jul. 22, 2021
Int. Cl. H10B 43/35 (2023.01); G11C 5/06 (2006.01); H10B 43/10 (2023.01)
CPC H10B 43/35 (2023.02) [G11C 5/063 (2013.01); H10B 43/10 (2023.02)] 17 Claims
OG exemplary drawing
 
1. A method for manufacturing a non-volatile memory device, the method comprising:
forming a trench extending vertically in a semiconductor well of a semiconductor substrate;
forming a source region at a bottom of the trench;
forming a gate dielectric layer around sidewalls of the trench;
forming, in the trench, a selection gate, the gate dielectric layer disposed between the semiconductor well and the selection gate;
forming a dielectric area on the sidewalls of the trench above the selection gate, the dielectric area comprising two charge trapping dielectric interfaces; and
forming, above the selection gate in the trench, a control gate, the control gate being laterally surrounded by the two charge trapping dielectric interfaces.