US 11,943,930 B2
Semiconductor memory device and methods of manufacturing and operating the same
Dong Uk Lee, Icheon-si (KR); and Hae Chang Yang, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jun. 14, 2023, as Appl. No. 18/334,583.
Application 18/334,583 is a division of application No. 17/898,932, filed on Aug. 30, 2022, granted, now 11,723,206.
Application 17/898,932 is a division of application No. 17/174,171, filed on Feb. 11, 2021, granted, now 11,462,566, issued on Oct. 4, 2022.
Claims priority of application No. 10-2020-0107387 (KR), filed on Aug. 25, 2020.
Prior Publication US 2023/0345725 A1, Oct. 26, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 13/00 (2006.01); G11C 16/10 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 43/27 (2023.02) [G11C 13/0004 (2013.01); G11C 13/0069 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); H10B 41/27 (2023.02); H10B 63/34 (2023.02); H10B 63/845 (2023.02); H10N 70/231 (2023.02); G11C 2213/75 (2013.01)] 2 Claims
OG exemplary drawing
 
1. A method of operating a semiconductor memory device, the method comprising:
performing a program operation on a plurality of memory cells each including a channel layer, a tunnel insulating layer, an emission preventing layer, a charge storage layer, a blocking insulating layer, and a compensation charge storage layer in response to a program command;
suspending the program operation in response to a suspend command received from outside of the semiconductor memory device, and applying a positive voltage to bit lines or a source line, connected to the memory cells, during a suspend period; and
re-performing the suspended program operation in response to a resume command received from outside of the semiconductor memory device.