US 11,943,924 B2
Void formation for charge trap structures
Chris M. Carlson, Nampa, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 22, 2021, as Appl. No. 17/181,901.
Application 16/452,292 is a division of application No. 15/675,197, filed on Aug. 11, 2017, granted, now 10,446,572.
Application 17/181,901 is a continuation of application No. 16/452,292, filed on Jun. 25, 2019, granted, now 10,937,802.
Prior Publication US 2021/0202521 A1, Jul. 1, 2021
Int. Cl. H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 29/40117 (2019.08); H01L 29/4234 (2013.01); H01L 29/512 (2013.01); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of forming a memory device, the method comprising:
forming a layered structure above a conductive region, with the layered structure having a vertical opening bounded by a sidewall;
forming, on and contacting the sidewall, material for dielectric barriers for a vertical arrangement of multiple charge trap structures, the material for dielectric barriers structured as a nanolaminate of multiple regions of different material compositions, with each charge trap structure having a charge trap region separated from a portion of the material for dielectric barriers by a dielectric blocking region; and
forming gates of the multiple charge trap structures, with the gates of adjacent charge trap structures separated by a void, each void having the material for dielectric barriers as a portion of a boundary of the void, with the material for dielectric barriers continuously extending vertically between and as a part of the multiple charge trap structures in the formed memory device.