US 11,943,917 B2
Stacked-type semiconductor memory device
Satoshi Nagashima, Yokkaichi (JP); Tatsuya Kato, Yokkaichi (JP); and Wataru Sakamoto, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on May 26, 2021, as Appl. No. 17/331,147.
Application 17/331,147 is a continuation of application No. 15/706,559, filed on Sep. 15, 2017, granted, now 11,049,868.
Application 15/706,559 is a continuation of application No. PCT/JP2015/063066, filed on May 1, 2015.
Prior Publication US 2021/0288057 A1, Sep. 16, 2021
Int. Cl. H10B 41/27 (2023.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 29/788 (2006.01); H10B 41/30 (2023.01)
CPC H10B 41/27 (2023.02) [G11C 16/0483 (2013.01); G11C 16/10 (2013.01); H01L 21/76885 (2013.01); H01L 23/528 (2013.01); H01L 29/7889 (2013.01); H10B 41/30 (2023.02)] 11 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a substrate;
a first wiring provided above the substrate and extending in a first direction parallel to a surface of the substrate;
a second wiring provided above the substrate and extending in the first direction, the first wiring and the second wiring being arranged at a second direction parallel to the surface of the substrate, the second direction crossing the first direction;
a first semiconductor pillar extending in a third direction away from the substrate;
a second semiconductor pillar extending in the third direction, the first semiconductor pillar and the second semiconductor pillar being arranged at the second direction;
a first memory cell provided on a side surface of the first semiconductor pillar, the first memory cell being provided between the first semiconductor pillar and the first wiring in the second direction, and the first memory cell being controllable by the first wiring;
a second memory cell provided on another side surface of the first semiconductor pillar, the second memory cell facing the first memory cell via the first semiconductor pillar in the second direction, the second memory cell being controllable by the second wiring;
a third memory cell provided on a side surface of the second semiconductor pillar, the third memory cell being controllable by applying a voltage to a first signal line electrically connected to the second wiring;
a first insulating layer being in contact with a first end portion of the second wiring in the first direction;
a third wiring provided above the substrate and extending in the first direction, the second wiring and the third wiring being arranged at the second direction;
a fourth memory cell provided on another side surface of the second semiconductor pillar, the fourth memory cell facing the third memory cell via the second semiconductor pillar in the second direction, the fourth memory cell being controllable by the third wiring; and
a second insulating layer being in contact with a second end portion of the third wiring in the first direction, the second insulating layer being provided at a different location away from the first insulating layer in the first direction and the second direction.