US 11,943,912 B2
Semiconductor device including buried gate structure and method for fabricating the same
Dong-Soo Kim, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jun. 20, 2022, as Appl. No. 17/844,111.
Application 16/737,612 is a division of application No. 15/857,016, filed on Dec. 28, 2017, granted, now 10,553,590, issued on Feb. 4, 2020.
Application 17/844,111 is a continuation of application No. 16/737,612, filed on Jan. 8, 2020, granted, now 11,393,824.
Claims priority of application No. 10-2017-0065959 (KR), filed on May 29, 2017.
Prior Publication US 2022/0320102 A1, Oct. 6, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/76 (2006.01); H01L 21/28 (2006.01); H01L 21/3213 (2006.01); H01L 21/3215 (2006.01); H01L 21/762 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 12/00 (2023.01); H01L 21/3105 (2006.01)
CPC H10B 12/34 (2023.02) [H01L 21/28088 (2013.01); H01L 21/28176 (2013.01); H01L 21/28194 (2013.01); H01L 21/32136 (2013.01); H01L 21/32155 (2013.01); H01L 21/76224 (2013.01); H01L 29/4236 (2013.01); H01L 29/4966 (2013.01); H01L 29/4983 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H10B 12/053 (2023.02); H10B 12/056 (2023.02); H10B 12/36 (2023.02); H01L 21/31053 (2013.01); H01L 29/517 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a gate trench that is extended into a semiconductor substrate;
a gate dielectric layer formed in the gate trench to cover an inside surface of the gate trench;
a crystallization delay layer disposed over the gate dielectric layer;
a gate electrode disposed over the crystallization delay layer to fill a lower part of the gate trench; and
an interface layer disposed between the crystallization delay layer and the gate dielectric layer;
wherein the gate electrode includes first crystal grains and second crystal grains in a columnar structure;
wherein the first crystal grains are free of voids at an interface between the gate electrode and the crystallization delay layer formed by a crystal grain growth of an amorphous material,
wherein the second crystal grains are formed by a crystal grain growth of a polycrystalline material, and wherein said crystal growth includes annealing the amorphous and the polycrystalline materials at a temperature of from 300 *C to 1100 *C; and
wherein the interface layer and the crystallization delay layer include a nitrogen-containing material, and the crystallization delay layer includes a higher nitrogen concentration than the interface layer.