US 11,943,864 B2
Stretchable/conformable electronic and optoelectronic circuits, methods, and applications
Christopher Kyle Renshaw, Orlando, FL (US); and Zhao Ma, Orlando, FL (US)
Assigned to University of Central Florida Research Foundation, Inc., Orlando, FL (US)
Filed by University of Central Florida Research Foundation, Inc., Orlando, FL (US)
Filed on Jan. 6, 2023, as Appl. No. 18/094,082.
Application 18/094,082 is a continuation of application No. 17/107,424, filed on Nov. 30, 2020, granted, now 11,570,892.
Application 17/107,424 is a continuation of application No. 15/948,065, filed on Apr. 9, 2018, granted, now 10,856,413, issued on Dec. 1, 2020.
Claims priority of provisional application 62/482,936, filed on Apr. 7, 2017.
Prior Publication US 2023/0403792 A1, Dec. 14, 2023
Int. Cl. H05K 1/03 (2006.01); G02B 13/00 (2006.01); H01L 27/146 (2006.01); H05K 1/18 (2006.01); H10K 77/10 (2023.01); H10K 85/10 (2023.01); H10K 102/00 (2023.01)
CPC H05K 1/0393 (2013.01) [G02B 13/0085 (2013.01); H01L 27/14627 (2013.01); H10K 77/111 (2023.02); H10K 85/111 (2023.02); H05K 1/189 (2013.01); H10K 2102/311 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A method comprising:
fabricating a wafer-based circuit including a plurality of circuit elements distributed across top surfaces of a plurality of spatially-separated wafer segments;
fabricating one or more through-silicon vias to electrically connect at least some of the plurality of circuit elements to interconnect points on a bottom surface of the wafer;
fabricating metal pillars on at least some of the interconnect points to extend these contacts vertically from the bottom surface of the wafer;
applying a polymer layer to the bottom surface of the wafer to form a backplane;
patterning an interconnect layer on top of the polymer layer, wherein the interconnect layer provides electrical connections between at least some of the metal pillars;
segmenting the wafer into a plurality of spatially-separated wafer segments, wherein at least one of spacings between the plurality of wafer segments or orientations of the plurality of wafer segments is adjustable by at least one of stretching or flexing the backplane.