US 11,943,728 B2
Clock synchronization for high speed asynchronous serial interfaces
Garry Z Gu, Manalapan, NJ (US)
Assigned to BAE Systems Information and Electronic Systems Integration Inc., Nashua, NH (US)
Filed by BAE SYSTEMS Information and Electronic Systems Integration Inc., Nashua, NH (US)
Filed on Oct. 7, 2021, as Appl. No. 17/496,017.
Prior Publication US 2023/0110448 A1, Apr. 13, 2023
Int. Cl. H04W 56/00 (2009.01)
CPC H04W 56/001 (2013.01) 20 Claims
OG exemplary drawing
 
1. A method for clock synchronization for use in high speed asynchronous serial interfaces, comprising:
on a first device:
receiving an ingress traffic from a second device;
decoding the ingress traffic using 8B10B;
splitting, via a traffic splitter, the ingress traffic in to an ingress regular traffic and a calibration feedback traffic;
processing the calibration feedback traffic via a calibration message receiver;
tuning a clock frequency based on the calibration feedback;
encoding a signal comprising at least one active message and an idle traffic using 8B10B to form a stream of K28.5 characters;
transmitting to the second device a signal comprising the encoded at least one active message and the idle traffic with an adjusted frequency; and
repeating preceding for a plurality of sample intervals, thereby reducing a probability of data sampling failure for high speed asynchronous serial interfaces.