US 11,943,554 B2
Imaging device operated by switching between product-sum operation
Seiichi Yoneda, Kanagawa (JP); Yusuke Negoro, Osaka (JP); and Hidetomo Kobayashi, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/605,817
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed Apr. 14, 2020, PCT No. PCT/IB2020/053483
§ 371(c)(1), (2) Date Oct. 22, 2021,
PCT Pub. No. WO2020/222059, PCT Pub. Date Nov. 5, 2020.
Claims priority of application No. 2019-087002 (JP), filed on Apr. 29, 2019; application No. 2019-088854 (JP), filed on May 9, 2019; application No. 2019-102209 (JP), filed on May 31, 2019; application No. 2019-107367 (JP), filed on Jun. 7, 2019; application No. 2019-137469 (JP), filed on Jul. 26, 2019; and application No. 2019-159378 (JP), filed on Sep. 2, 2019.
Prior Publication US 2022/0201234 A1, Jun. 23, 2022
Int. Cl. H04N 25/77 (2023.01); H01L 27/146 (2006.01); H01L 29/786 (2006.01); H04N 25/46 (2023.01); H04N 25/79 (2023.01)
CPC H04N 25/77 (2023.01) [H01L 27/14616 (2013.01); H04N 25/46 (2023.01); H04N 25/79 (2023.01); H01L 29/7869 (2013.01)] 11 Claims
OG exemplary drawing
 
1. An imaging device comprising a pixel block, a first circuit, and a second circuit,
wherein the pixel block comprises a plurality of pixels arranged in a matrix,
wherein the plurality of pixels are electrically connected to the second circuit,
wherein the first circuit has a function of selecting pixels arranged in one row of the plurality of pixels,
wherein the first circuit has a function of selecting pixels arranged in a plurality of consecutive rows of the plurality of pixels,
wherein the first circuit has a function of changing the number of rows to be selected,
wherein the pixel has a function of generating first data,
wherein the pixel has a function of generating second data by adding a predetermined potential to the first data,
wherein the second circuit has a function of generating third data corresponding to a sum of the first data generated by the plurality of pixels,
wherein the second circuit generates fourth data by adding, to the third data, a potential corresponding to a sum of the second data generated by the plurality of pixels
wherein the first circuit is a shift register circuit comprising a first logic circuit, a second logic circuit, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor,
wherein an output terminal of the first logic circuit is electrically connected to one of a source and a drain of the twelfth transistor,
wherein an output terminal of the second logic circuit is electrically connected to one of a source and a drain of the thirteenth transistor,
wherein the other of the source and the drain of the twelfth transistor is electrically connected to one of a source and a drain of the fourteenth transistor,
wherein the other of the source and the drain of the fourteenth transistor is electrically connected to the other of the source and the drain of the thirteenth transistor,
wherein the other of the source and the drain of the twelfth transistor is electrically connected to one of a source and a drain of the fifteenth transistor, and
wherein the other of the source and the drain of the fifteenth transistor is electrically connected to a power supply line.