US 11,943,130 B2
Aggregation-based speed testing
Karthik Subramanian, Germantown, MD (US); Reynald Dupuis, Germantown, MD (US); and Hans Joerg Wolf, Woodbine, MD (US)
Assigned to VIAVI SOLUTIONS INC., Chandler, AZ (US)
Filed by VIAVI SOLUTIONS INC., Chandler, AZ (US)
Filed on Oct. 6, 2022, as Appl. No. 17/961,179.
Application 17/961,179 is a division of application No. 16/983,761, filed on Aug. 3, 2020, granted, now 11,516,107.
Prior Publication US 2023/0025255 A1, Jan. 26, 2023
Int. Cl. H04L 43/50 (2022.01); G06F 11/34 (2006.01); H04L 43/0888 (2022.01); H04L 43/0894 (2022.01); H04L 43/16 (2022.01)
CPC H04L 43/50 (2013.01) [G06F 11/3409 (2013.01); H04L 43/0888 (2013.01); H04L 43/0894 (2013.01); H04L 43/16 (2013.01); G06F 2201/875 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An apparatus comprising:
at least one hardware processor;
a test speed analyzer, executed by the at least one hardware processor, to
ascertain a test speed that corresponds to a maximum specified data transfer rate for a data transmission link that is to be tested;
a test range generator, executed by the at least one hardware processor, to
determine a maximum specified processing speed of at least one test processor of a test instrument,
determine whether the maximum specified processing speed of the at least one test processor of the test instrument is less than the test speed, and
based on a determination that the maximum specified processing speed of the at least one test processor of the test instrument is less than the test speed, divide the test speed into a plurality of test ranges corresponding to the at least one test processor, wherein a total value of the plurality of test ranges is at least equal to the test speed;
a test performer, executed by the at least one hardware processor, to
perform, for the at least one test processor, a test corresponding to each test range of the plurality of test ranges, and
obtain an intermediate test result for each test range of the plurality of test ranges; and
a test result generator, executed by the at least one hardware processor, to
generate, based on aggregation of each intermediate test result for each test range of the plurality of test ranges, an aggregated test result that represents an actual speed associated with the data transmission link.