CPC H03M 7/4093 (2013.01) | 20 Claims |
1. A circuit to compress data comprising:
a first plurality of switch circuits having inputs coupled to a plurality of values of an input vector, the first plurality of switch circuits further having control inputs coupled to bits of a bit mask to selectively couple multiple values of the plurality of values on one input of each of the first plurality of switch circuits to corresponding outputs of the first plurality of switch circuits;
a second plurality of switch circuits having inputs coupled to the multiple values on the outputs of the first plurality of switch circuits; and
a logic circuit having inputs coupled to the outputs of the first plurality of switch circuits and having outputs coupled to select inputs of the second plurality of switch circuits, the logic circuit detecting particular values on the outputs of the first plurality of switch circuits and configuring the second plurality of switch circuits to each output one of the particular values.
|