US 11,942,957 B2
Firmware-based interleaved-ADC gain calibration and hardware-thresholding enhancements
Kevin R. Rivas-Rivera, San Diego, CA (US); and Tao Conrad, Bedford, MA (US)
Assigned to Analog Devices, Inc., Wilmington, MA (US)
Filed by Analog Devices, Inc., Wilmington, MA (US)
Filed on Feb. 14, 2022, as Appl. No. 17/670,943.
Claims priority of provisional application 63/149,645, filed on Feb. 15, 2021.
Prior Publication US 2022/0263514 A1, Aug. 18, 2022
Int. Cl. H03M 1/06 (2006.01); H03M 1/10 (2006.01); H03M 1/12 (2006.01)
CPC H03M 1/0604 (2013.01) [H03M 1/1014 (2013.01); H03M 1/1215 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method to extract interleaving gain errors of a time-interleaved analog-to-digital converter having sub-analog-to-digital converters (subADCs) to sample an analog input signal in a time-interleaved manner, the method comprising:
capturing a first data block of first output samples of a first subADC of the subADCs;
evaluating whether one or more of the first output samples meet an amplitude condition;
estimating a first power based on at least some of the first output samples of the first data block;
evaluating whether the first power meets a power condition;
qualifying, by a qualifier, whether first data block is suitable for interleaving gain error extraction;
determining to proceed with extraction of a first interleaving gain error based on a memory storing a number of previous qualifier results from the qualifier; and
estimating the first interleaving gain error based the first power and a second power estimated based on second output samples of a second subADC of the subADCs.