CPC H03L 7/0805 (2013.01) [H03L 7/085 (2013.01)] | 25 Claims |
1. An apparatus comprising:
a reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value;
a droop detection circuit that converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal;
a digital frequency-locked loop (DFLL) providing a clock signal for synchronizing circuitry within a domain of the monitored supply voltage; and
a DFLL control circuit that, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.
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