US 11,942,953 B2
Droop detection and control of digital frequency-locked loop
Kaushik Mazumdar, Waltham, MA (US); Joyce Cheuk Wai Wong, Toronto (CA); Naeem Ibrahim Ally, Mississauga (CA); and Stephen Victor Kosonocky, Fort Collins, CO (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US); and ATI Technologies ULC, Markham (CA)
Filed on Dec. 21, 2021, as Appl. No. 17/557,590.
Prior Publication US 2023/0198528 A1, Jun. 22, 2023
Int. Cl. H03L 7/08 (2006.01); H03L 7/085 (2006.01)
CPC H03L 7/0805 (2013.01) [H03L 7/085 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a reference signal generator that receives a digital value and produces a pulse-density modulated signal based on the digital value;
a droop detection circuit that converts the pulse-density modulated signal to an analog signal, compares the analog signal to a monitored supply voltage, and responsive to detecting a droop of the monitored supply voltage below a designated value relative to the analog signal, produces a droop detection signal;
a digital frequency-locked loop (DFLL) providing a clock signal for synchronizing circuitry within a domain of the monitored supply voltage; and
a DFLL control circuit that, responsive to receiving the droop detection signal, causes the DFLL to slow the clock signal.