US 11,942,943 B1
Duty cycle adjustment circuit and method thereof
Chia-Liang (Leon) Lin, Fremont, CA (US)
Assigned to REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed by Realtek Semiconductor Corp., Hsinchu (TW)
Filed on Oct. 6, 2022, as Appl. No. 17/938,360.
Int. Cl. H03K 7/08 (2006.01); H03K 3/017 (2006.01); H03K 17/687 (2006.01); H03K 17/693 (2006.01); H03K 19/20 (2006.01); H03M 7/16 (2006.01)
CPC H03K 3/017 (2013.01) [H03K 7/08 (2013.01); H03K 17/6872 (2013.01); H03K 17/693 (2013.01); H03K 19/20 (2013.01); H03M 7/165 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A duty-cycle adjustment circuit comprising:
a conditional inversion circuit configured to receive an input clock and output a conditionally inverted clock in accordance with an inversion enable signal; and
a one-directional duty adjustment circuit comprising an uneven clock buffer and an uneven clock multiplexer (UCM) chain comprising NUCMs, where Nis an integer greater than 1, that are cascaded and controlled by a N-bit control code, wherein each of said NUCMs receives a respective first input from either the conditional inversion circuit or a respective preceding UCM, and a respective second input from either a respective succeeding UCM or the uneven clock buffer, and outputs a respective first output to either a respective succeeding UCM or the uneven clock buffer, and a respective second output either as an output clock or to a respective preceding UCM, in accordance with a respective bit of the N-bit control code.