US 11,942,935 B2
Programmable logic block with multiple types of programmable arrays and flexible clock selection
Mark Wallis, Mouans Sartoux (FR); Jean-Francois Link, Trets (FR); and Joran Pantel, Marseilles (FR)
Assigned to STMicroelectronics (Rousset) SAS, Rousset (FR)
Filed by STMICROELECTRONICS (ROUSSET) SAS, Rousset (FR)
Filed on Jul. 8, 2022, as Appl. No. 17/861,067.
Prior Publication US 2024/0014819 A1, Jan. 11, 2024
Int. Cl. H03K 19/17724 (2020.01); H03K 19/173 (2006.01); H03K 19/17736 (2020.01); H03K 19/20 (2006.01)
CPC H03K 19/17724 (2013.01) [H03K 19/1737 (2013.01); H03K 19/1774 (2013.01); H03K 19/17744 (2013.01); H03K 19/20 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a plurality of input signals at a first multiplexer of first logic cell of a programmable logic array;
providing a subset of the plurality of input signals to a second multiplexer;
receiving a global clock signal at a first input of an AND gate;
receiving a selected input signal of the plurality of input signals at a second input of the AND gate;
outputting the selected input signal from the multiplexer to a second input of the AND gate, and
supplying a clock signal from the AND gate to a clock input terminal of a flip-flop of the first logic cell.