US 11,942,904 B2
Systems and methods for digital predistortion to mitigate power amplifier bias circuit effects
Hongzhi Zhao, Los Gatos, CA (US); Xing Zhao, San Ramon, CA (US); Vincent C. Barnes, El Paso, TX (US); Xiaohan Chen, Sunnyvale, CA (US); and Hemang M. Parekh, San Jose, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by Xilinx, Inc., San Jose, CA (US)
Filed on Aug. 16, 2021, as Appl. No. 17/402,892.
Prior Publication US 2023/0046588 A1, Feb. 16, 2023
Int. Cl. H03F 1/32 (2006.01); H03F 3/21 (2006.01); H03G 1/00 (2006.01)
CPC H03F 1/3247 (2013.01) [H03F 3/21 (2013.01); H03G 1/0005 (2013.01); H03F 2201/3227 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A digital predistortion (DPD) system, comprising:
an input configured to receive an input signal;
a first signal path configured to generate a first signal based on the input signal;
an error model provider configured to generate an error model signal modeled after a gate bias error voltage associated with the DPD system, wherein the error model provider includes a time counter;
a first combiner configured to combine the first signal and the error model signal to generate a first intermediate signal; and
an output signal based at least on the first intermediate signal.