CPC H03F 1/3247 (2013.01) [H03F 3/21 (2013.01); H03G 1/0005 (2013.01); H03F 2201/3227 (2013.01)] | 20 Claims |
1. A digital predistortion (DPD) system, comprising:
an input configured to receive an input signal;
a first signal path configured to generate a first signal based on the input signal;
an error model provider configured to generate an error model signal modeled after a gate bias error voltage associated with the DPD system, wherein the error model provider includes a time counter;
a first combiner configured to combine the first signal and the error model signal to generate a first intermediate signal; and
an output signal based at least on the first intermediate signal.
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