US 11,942,696 B1
Integrated circuit chips for a phased array system including programmable on-chip element swapping, channel swapping, and/or phase rotation circuitry
Lewis N. Cohen, San Diego, CA (US); Robert J. McMorrow, Concord, MA (US); Jason Leo Durbin, San Diego, CA (US); and Vipul Jain, Irvine, CA (US)
Assigned to Anokiwave, Inc., San Diego, CA (US)
Filed by Anokiwave, Inc., San Diego, CA (US)
Filed on May 5, 2022, as Appl. No. 17/737,567.
Claims priority of provisional application 63/185,044, filed on May 6, 2021.
Int. Cl. H01Q 3/34 (2006.01); G06K 7/10 (2006.01); G06K 19/073 (2006.01); H01Q 1/22 (2006.01)
CPC H01Q 3/34 (2013.01) [G06K 7/10019 (2013.01); G06K 19/07345 (2013.01); H01Q 1/2208 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An RFIC chip comprising:
a common interface circuit including a first common interface and a second common interface;
at least one element interface circuit coupled to the common interface circuit, each element interface circuit including a first element interface including a first 180 degree phase shifter and a second element interface including a second 180 degree phase shifter;
programmable channel swapping circuitry configured to selectively switch between a first channel configuration and a second channel configuration based on a channel swap parameter, the first channel configuration coupling the first common interface to the first element interface of each element interface circuit and coupling the second common interface to the second element interface of each element interface circuit, the second channel configuration coupling the first common interface to the second element interface of each element interface circuit and coupling the second common interface to the first element interface of each element interface circuit;
programmable phase rotation circuitry configured to selectively enable or disable the 180 degree phase shifter of each element interface based on a corresponding element rotation parameter;
at least one memory storing, for each element interface circuit, a first set of gain and phase parameters and a second set of gain and phase parameters; and
parameter swapping circuitry configured to selectively switch each element interface circuit between a first parameter configuration corresponding to the first channel configuration and a second parameter configuration corresponding to the second channel configuration based on the channel swap parameter, the first parameter configuration providing the first set of parameters to the first element interface and providing the second set of parameters to the second element interface, the second parameter configuration providing the first set of parameters to the second element interface and providing the second set of parameters to the first element interface.