US 11,942,579 B2
Light emitting device and adaptive driving beam headlamp
Toru Taruki, Tokushima (JP); and Daisuke Sanga, Tokushima (JP)
Assigned to NICHIA CORPORATION, Anan (JP)
Filed by NICHIA CORPORATION, Anan (JP)
Filed on Oct. 15, 2021, as Appl. No. 17/502,939.
Application 17/502,939 is a continuation of application No. 15/893,411, filed on Feb. 9, 2018, granted, now 11,177,417.
Claims priority of application No. 2017-024482 (JP), filed on Feb. 13, 2017; and application No. 2017-204140 (JP), filed on Oct. 23, 2017.
Prior Publication US 2022/0037564 A1, Feb. 3, 2022
Int. Cl. H01L 33/50 (2010.01); H01L 27/15 (2006.01); H01L 33/00 (2010.01); H01L 33/08 (2010.01); H01L 33/22 (2010.01); H01L 33/36 (2010.01); H01L 33/38 (2010.01); H01L 33/62 (2010.01); F21S 41/153 (2018.01); F21S 41/19 (2018.01); F21Y 115/10 (2016.01)
CPC H01L 33/505 (2013.01) [H01L 27/156 (2013.01); H01L 33/0093 (2020.05); H01L 33/08 (2013.01); H01L 33/22 (2013.01); H01L 33/36 (2013.01); H01L 33/382 (2013.01); H01L 33/502 (2013.01); H01L 33/62 (2013.01); F21S 41/153 (2018.01); F21S 41/192 (2018.01); F21Y 2115/10 (2016.08); H01L 2933/0041 (2013.01); H01L 2933/0066 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A light emitting device comprising:
a base;
a first terminal and a second terminal located at an upper surface of the base;
a light emitting element array chip mounted on the upper surface of the base such that the light emitting element array chip is located between the first terminal and the second terminal, the light emitting element array chip comprising:
a plurality of light emitting elements,
a support substrate having a continuous upper surface that supports the plurality of light emitting elements,
a multilayer wiring structure disposed above the support substrate and comprising a plurality of first wirings, a plurality of second wirings, and an inter-wiring insulating film, wherein the plurality of first wirings are located above the plurality of second wirings with portions of the inter-wiring insulating film located therebetween, wherein each of the light emitting elements is arranged above and electrically connected to one of the first wirings and one of the second wirings;
a plurality of wires including a plurality of first wires connecting the plurality of first wirings to the first terminal, and a plurality of second wires connecting the plurality of second wirings to the second terminal; and
a phosphor layer directly covering the light emitting element array chip so as to collectively cover surfaces of the plurality of light emitting elements, wherein an average layer thickness of the phosphor layer is 50 μm or less.