US 11,942,557 B2
Nanosheet transistor with enhanced bottom isolation
Lan Yu, Voorheesville, NY (US); Andrew M. Greene, Slingerlands, NY (US); Wenyu Xu, Albany, NY (US); and Heng Wu, Guilderland, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on May 3, 2021, as Appl. No. 17/246,762.
Prior Publication US 2022/0352386 A1, Nov. 3, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/78696 (2013.01) [H01L 29/0665 (2013.01); H01L 29/41775 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor nanosheet device comprising:
semiconductor channel layers vertically aligned and stacked one on top of another, the semiconductor channel layers separated by a work function metal; and
a second layer sandwiched between two first layers, the second layer and the two first layers are below the semiconductor channel layers and above a substrate, wherein vertical side surfaces of the semiconductor channel layers are vertically aligned with vertical side surfaces of an upper layer of the two first layers, wherein a combined thickness of the second layer and the two first layers is approximately the same as a thickness of the work function metal between the semiconductor channel layers.