US 11,942,555 B2
Semiconductor device and manufacturing method thereof
Shunpei Yamazaki, Tokyo (JP); Junichi Koezuka, Tochigi (JP); Masami Jintyou, Tochigi (JP); and Yukinori Shima, Tatebayashi (JP)
Assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Kanagawa-ken (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Apr. 13, 2023, as Appl. No. 18/134,185.
Application 15/907,315 is a division of application No. 14/610,336, filed on Jan. 30, 2015, granted, now 9,929,279, issued on Mar. 27, 2018.
Application 18/134,185 is a continuation of application No. 17/320,557, filed on May 14, 2021, granted, now 11,640,996, issued on May 2, 2023.
Application 17/320,557 is a continuation of application No. 16/658,196, filed on Oct. 21, 2019, granted, now 11,011,648, issued on May 18, 2021.
Application 16/658,196 is a continuation of application No. 15/907,315, filed on Feb. 28, 2018, granted, now 10,680,116, issued on Jun. 9, 2020.
Claims priority of application No. 2014-020061 (JP), filed on Feb. 5, 2014; and application No. 2014-041446 (JP), filed on Mar. 4, 2014.
Prior Publication US 2023/0307547 A1, Sep. 28, 2023
Int. Cl. H01L 29/786 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7869 (2013.01) [H01L 29/42384 (2013.01); H01L 29/66969 (2013.01); H01L 29/78606 (2013.01); H01L 29/78618 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device comprising a pixel portion,
wherein the pixel portion comprises a transistor and a light emitting element electrically connected to the transistor,
wherein the transistor comprises:
an oxide semiconductor layer comprising In, Ga, and Zn;
a gate insulating layer over the oxide semiconductor layer;
a gate electrode overlapping with the oxide semiconductor layer with the gate insulating layer provided therebetween, the gate electrode comprising a first layer and a second layer provided over the first layer;
a first insulating layer over the gate electrode, the first insulating layer having a region being in contact with a top surface of the gate insulating layer; and
a first conductive layer over the first insulating layer, a part of the first conductive layer connected to the oxide semiconductor layer through an opening provides the first insulating layer,
wherein in a cross-sectional view parallel to a channel length direction of the transistor, an end portion of the first layer of the gate electrode is positioned on an outer side than an end portion of the second layer of the gate electrode,
wherein in the cross-sectional view parallel to the channel length direction of the transistor, the oxide semiconductor layer comprises:
a channel formation region;
a first region being adjacent to the channel formation region and being in contact with the gate insulating layer;
a second region being adjacent to the first region and being in contact with the first insulating layer; and
a third region being in contact with the part of the first conductive layer, and wherein the first region is thicker than the second region and the third region.