US 11,942,554 B2
Semiconductor device, display device including the semiconductor device, and an electronic device including the semiconductor device
Yasuharu Hosaka, Tochigi (JP); Yukinori Shima, Gunma (JP); Masataka Nakada, Tochigi (JP); and Masami Jintyou, Tochigi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Jan. 27, 2022, as Appl. No. 17/585,645.
Application 17/585,645 is a continuation of application No. 15/774,930, granted, now 11,329,166, previously published as PCT/IB2016/056731, filed on Nov. 9, 2016.
Claims priority of application No. 2015-227617 (JP), filed on Nov. 20, 2015; and application No. 2015-237207 (JP), filed on Dec. 4, 2015.
Prior Publication US 2022/0149205 A1, May 12, 2022
Int. Cl. H01L 29/12 (2006.01); H01L 21/426 (2006.01); H01L 27/12 (2006.01); H01L 29/04 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); G02F 1/1368 (2006.01); H10K 50/115 (2023.01); H10K 59/12 (2023.01); H10K 59/40 (2023.01)
CPC H01L 29/7869 (2013.01) [H01L 29/04 (2013.01); H01L 29/423 (2013.01); H01L 29/42384 (2013.01); H01L 29/49 (2013.01); H01L 29/4908 (2013.01); H01L 29/66969 (2013.01); H01L 29/78633 (2013.01); H01L 29/78648 (2013.01); G02F 1/1368 (2013.01); H01L 21/426 (2013.01); H01L 27/1225 (2013.01); H10K 50/115 (2023.02); H10K 59/12 (2023.02); H10K 59/40 (2023.02)] 3 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first conductive film;
a first insulating film over the first conductive film;
a first semiconductor film, having a region overlapping with the first conductive film, over the first insulating film;
a second insulating film having a region in contact with a top surface of the first semiconductor film;
a second conductive film, having a region overlapping with the first semiconductor film, over the second insulating film;
a third insulating film comprising silicon nitride and having a region in contact with a top surface of the second conductive film, a region in contact with a side surface of the second conductive film, and a region in contact with a top surface of the second insulating film;
a fourth insulating film comprising silicon oxide and having a region in contact with a top surface of the third insulating film;
a fifth insulating film comprising an organic material and having a region in contact with a top surface of the fourth insulating film;
a third conductive film and a fourth conductive film over the fifth insulating film;
a pixel electrode of a liquid crystal element electrically connected to the fourth conductive film; and
a common electrode overlapping with the pixel electrode and the third conductive film,
wherein the first semiconductor film comprises a channel formation region of a transistor,
wherein the second conductive film is configured to function as a gate electrode of the transistor,
wherein the third conductive film is configured to function as one of a source electrode and a drain electrode of the transistor,
wherein the fourth conductive film is configured to function as the other of the source electrode and the drain electrode of the transistor,
wherein the third insulating film and the fourth insulating film comprise a first opening and a third opening,
wherein the fifth insulating film comprises a second opening overlapping with the first opening,
wherein in a cross-sectional view, an upper edge of the first opening is not aligned with a lower edge of the second opening,
wherein a diameter of the second opening at the lower edge of the second opening is larger than a diameter of the first opening at the upper edge of the first opening,
wherein the third conductive film has a region in contact with a top surface of the fifth insulating film and a region in contact with the top surface of the first semiconductor film in a region where the first opening and the second opening overlap with each other,
wherein a spacer overlaps with the first semiconductor film with the third conductive film provided therebetween,
wherein the first semiconductor film is in contact with the fourth conductive film in the third opening, and
wherein the pixel electrode overlaps with the third opening.