US 11,942,551 B2
Semiconductor devices
Jung Taek Kim, Yongin-si (KR); Seok Hoon Kim, Suwon-si (KR); Pan Kwi Park, Incheon (KR); Moon Seung Yang, Hwaseong-si (KR); Seo Jin Jeong, Incheon (KR); Min-Hee Choi, Suwon-si (KR); and Ryong Ha, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 5, 2021, as Appl. No. 17/519,967.
Claims priority of application No. 10-2020-0172433 (KR), filed on Dec. 10, 2020.
Prior Publication US 2022/0190168 A1, Jun. 16, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/78618 (2013.01) [H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a multi-channel active pattern;
a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode extending in a second direction different from the first direction;
a source/drain recess between an adjacent pair of the plurality of gate structures; and
a source/drain pattern on the multi-channel active pattern in the source/drain recess,
wherein the source/drain pattern includes:
a semiconductor liner layer including silicon-germanium and extending along the source/drain recess,
a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and
at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and
wherein the at least one or more semiconductor insertion layers have a three-dimensional saddle structure including a saddle point, a first saddle region on opposite sides of the saddle point in the second direction, and a second saddle region on opposite sides of the saddle point in the first direction.