US 11,942,545 B2
Semiconductor memory device
Yuta Sato, Yokohama Kanagawa (JP); Tomomasa Ueda, Yokohama Kanagawa (JP); Nobuyoshi Saito, Tokyo (JP); and Keiji Ikeda, Kawasaki Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jul. 27, 2022, as Appl. No. 17/875,376.
Application 17/875,376 is a continuation of application No. 17/198,682, filed on Mar. 11, 2021, granted, now 11,430,886.
Claims priority of application No. 2020-155889 (JP), filed on Sep. 16, 2020.
Prior Publication US 2022/0406934 A1, Dec. 22, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 27/12 (2006.01); H01L 27/13 (2006.01); H01L 29/24 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/7827 (2013.01) [H01L 27/1203 (2013.01); H01L 27/13 (2013.01); H01L 29/24 (2013.01); H01L 29/42356 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a first electrode;
a second electrode,
an oxide semiconductor layer provided between the first electrode and the second electrode, the oxide semiconductor layer being in contact with the first electrode, the oxide semiconductor layer containing zinc (Zn) and at least one first element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), and tin (Sn), and a chemical composition of the oxide semiconductor layer being different from a chemical composition of the first electrode and the second electrode;
a conductive layer provided between the oxide semiconductor layer and the second electrode, the conductive layer being in contact with the second electrode, the conductive layer containing oxygen (O) and at least one second element selected from the group consisting of indium (In), gallium (Ga), silicon (Si), aluminum (Al), tin (Sn), zinc (Zn), and titanium (Ti), and a chemical composition of the conductive layer being different from a chemical composition of the first electrode, the second electrode, and the oxide semiconductor layer;
a gate electrode;
a gate insulating layer provided between the oxide semiconductor layer and the gate electrode; and
a capacitor electronically connected to the first 30 electrode.