US 11,942,533 B2
Channel structures for semiconductor devices
Ding-Kang Shih, New Taipei (TW); and Pang-Yen Tsai, Jhu-bei (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 31, 2021, as Appl. No. 17/463,123.
Prior Publication US 2023/0061755 A1, Mar. 2, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/66795 (2013.01) [H01L 21/823431 (2013.01); H01L 29/0665 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a superlattice structure comprising a plurality of first nanostructured layers and a plurality of second nanostructured layers on a substrate;
removing the plurality of second nanostructured layers to form a plurality of gate openings;
forming a germanium epitaxial layer on the plurality of first nanostructured layers at a first temperature;
performing a temperature ramping process for a first period of time to increase the first temperature to a second temperature; and
annealing the germanium epitaxial layer at the second temperature for a second period of time to form a cladding layer surrounding the plurality of first nanostructured layers.