US 11,942,518 B2
Reduced interfacial area III-nitride material semiconductor structures
Timothy E. Boles, Tyngsboro, MA (US); and Wayne Mack Struble, Franklin, MA (US)
Assigned to MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC., Lowell, MA (US)
Filed by MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed on Jun. 1, 2021, as Appl. No. 17/335,521.
Application 17/335,521 is a continuation of application No. 16/039,866, filed on Jul. 19, 2018, granted, now 11,038,023.
Prior Publication US 2021/0296481 A1, Sep. 23, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/20 (2006.01); H01L 21/02 (2006.01); H01L 23/66 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 29/15 (2006.01); H01L 29/778 (2006.01); H01L 29/872 (2006.01)
CPC H01L 29/2003 (2013.01) [H01L 21/02381 (2013.01); H01L 21/02458 (2013.01); H01L 21/02505 (2013.01); H01L 21/0254 (2013.01); H01L 23/66 (2013.01); H01L 27/0211 (2013.01); H01L 27/0605 (2013.01); H01L 29/155 (2013.01); H01L 29/7787 (2013.01); H01L 29/872 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a III-nitride material region located over the substrate;
an ohmic contact over the III-nitride material region, the ohmic contact defining an ohmic contact interfacial area with the III-nitride material region; and
a gate electrode over the III-nitride material region, the gate electrode defining a gate electrode interfacial area with the III-nitride material region, wherein
the ohmic contact interfacial area is less than 50 times the gate electrode interfacial area.