US 11,942,488 B2
Display device and method of fabricating the same
Kyung Jin Jeon, Incheon (KR); So Young Koo, Yongin-si (KR); Eok Su Kim, Seoul (KR); Hyung Jun Kim, Seoul (KR); Joon Seok Park, Yongin-si (KR); and Jun Hyung Lim, Seoul (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed on Mar. 30, 2023, as Appl. No. 18/193,200.
Application 18/193,200 is a division of application No. 17/109,601, filed on Dec. 2, 2020, granted, now 11,626,426.
Claims priority of application No. 10-2020-0014723 (KR), filed on Feb. 7, 2020.
Prior Publication US 2023/0253415 A1, Aug. 10, 2023
Int. Cl. H01L 27/14 (2006.01); H01L 27/12 (2006.01); H10K 59/131 (2023.01)
CPC H01L 27/124 (2013.01) [H01L 27/1262 (2013.01); H10K 59/131 (2023.02)] 5 Claims
OG exemplary drawing
 
1. A method of fabricating a display device comprising a plurality of pixels and a first transistor and a second transistor in each of the pixels, the method comprising:
forming a first conductive layer, which comprises a first power wiring electrically connected to a first source/drain electrode of the first transistor, a lower light blocking pattern electrically connected to a second source/drain electrode of the first transistor and a data wiring electrically connected to a first source/drain electrode of the second transistor, on a substrate;
sequentially coating an insulating layer material, a semiconductor layer material and a gate insulating layer material on the substrate to cover the first conductive layer; and
etching the gate insulating layer material, the semiconductor layer material and the insulating layer material by using a halftone mask to pattern a gate insulating layer which comprises a gate insulating layer of the first transistor and a gate insulating layer of the second transistor, a semiconductor layer which comprises a semiconductor pattern of the first transistor and a semiconductor pattern of the second transistor, and an insulating layer which comprises a first insulating pattern having the same planar shape as the semiconductor pattern of the first transistor and a second insulating pattern having a same planar shape as the semiconductor pattern of the second transistor.