US 11,942,476 B2
Method for forming semiconductor device with helmet structure between two semiconductor fins
Kuo-Cheng Ching, Hsinchu County (TW); Shi-Ning Ju, Hsinchu (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jul. 15, 2022, as Appl. No. 17/866,365.
Application 17/007,786 is a division of application No. 16/103,721, filed on Aug. 14, 2018, granted, now 10,763,255, issued on Sep. 1, 2020.
Application 17/866,365 is a continuation of application No. 17/007,786, filed on Aug. 31, 2020, granted, now 11,393,814.
Prior Publication US 2022/0352157 A1, Nov. 3, 2022
Int. Cl. H01L 27/088 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/033 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 27/02 (2006.01); H01L 29/08 (2006.01); H01L 29/165 (2006.01); H01L 29/205 (2006.01); H01L 29/267 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0886 (2013.01) [H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/76224 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 27/0207 (2013.01); H01L 29/0847 (2013.01); H01L 29/66545 (2013.01); H01L 29/7848 (2013.01); H01L 21/0217 (2013.01); H01L 21/02271 (2013.01); H01L 21/0228 (2013.01); H01L 21/0274 (2013.01); H01L 21/0332 (2013.01); H01L 21/31053 (2013.01); H01L 21/32139 (2013.01); H01L 29/165 (2013.01); H01L 29/205 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a semiconductor fin on a substrate;
conformally forming a dielectric layer over the semiconductor fin;
depositing an oxide layer over the dielectric layer;
etching back the oxide layer to lower a top surface of the oxide layer to a level below a top surface of the semiconductor fin;
conformally forming a metal oxide layer over the semiconductor fin, the dielectric layer, and the etched back oxide layer;
planarizing the metal oxide layer and the dielectric layer to expose the semiconductor fin;
forming a gate structure extending across the semiconductor fin; and
forming source/drain regions on the semiconductor fin and on opposite sides of the gate structure.