US 11,942,474 B2
Parallel structure, method of manufacturing the same, and electronic device including the same
Huilong Zhu, Poughkeepsie, NY (US)
Assigned to INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES, Beijing (CN)
Filed by INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES, Beijing (CN)
Filed on Feb. 22, 2023, as Appl. No. 18/172,802.
Application 18/172,802 is a division of application No. 17/042,832, granted, now 11,631,669, previously published as PCT/CN2018/113040, filed on Oct. 31, 2018.
Claims priority of application No. 201811171611.7 (CN), filed on Oct. 8, 2018.
Prior Publication US 2023/0215865 A1, Jul. 6, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 21/77 (2017.01); H01L 25/065 (2023.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/088 (2013.01) [H01L 21/77 (2013.01); H01L 25/0657 (2013.01); H01L 29/66712 (2013.01); H01L 29/7802 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A method of manufacturing a parallel structure of semiconductor devices, comprising:
disposing a semiconductor stack on a substrate, wherein the semiconductor stack comprises a plurality of source/drain layers disposed sequentially in a vertical direction and two or more channel layers respectively disposed between respective pairs of adjacent ones of the source/drain layers;
patterning the semiconductor stack into a predetermined shape to define an active region;
forming gate stacks around at least part of outer peripheries of the respective channel layers;
forming an isolation layer on outer peripheries of the active region and the gate stack; and
forming a first electrically conductive channel, a second electrically conductive channel and a third electrically conductive channel on a sidewall of the isolation layer,
wherein, the method further comprises determining the pre-determined shape and a shape of the formed gate stacks, such that in each of the semiconductor devices, one of the source/drain layers on upper and lower sides of the corresponding channel layer passes through the isolation layer to contact the first electrically conductive channel, while the other one passes through the isolation layer to contact the second electrically conductive channel, and the corresponding gate stack passes through the isolation layer to contact the third electrically conductive channel.