US 11,942,466 B2
Memory device having multiple chips and method for manufacturing the same
Mutsumi Okajima, Yokkaichi Mie (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jun. 13, 2022, as Appl. No. 17/839,431.
Application 17/839,431 is a division of application No. 17/017,101, filed on Sep. 10, 2020, granted, now 11,387,227.
Claims priority of application No. 2020-052006 (JP), filed on Mar. 24, 2020.
Prior Publication US 2022/0310581 A1, Sep. 29, 2022
Int. Cl. H01L 25/00 (2006.01); H01L 21/02 (2006.01); H01L 23/00 (2006.01); H01L 25/18 (2023.01); H10B 12/00 (2023.01); H10B 61/00 (2023.01); G11C 11/16 (2006.01); G11C 11/407 (2006.01)
CPC H01L 25/50 (2013.01) [H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/18 (2013.01); G11C 11/161 (2013.01); G11C 11/407 (2013.01); H01L 21/02244 (2013.01); H01L 21/02258 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/8013 (2013.01); H01L 2924/1436 (2013.01); H10B 12/033 (2023.02); H10B 61/10 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A method for manufacturing a memory device, comprising:
forming an oxide layer on a first substrate by anodic oxidation, the oxide layer including a plurality of first holes arranged at first intervals and a plurality of second holes arranged at second intervals;
forming a plurality of memory units in the first holes, respectively and forming a plurality of first mark portions in the second holes, respectively;
forming a first insulating layer on the oxide layer, the first insulating layer including a first pad in a first surface of the first insulating layer; and
bonding the first surface of the first insulating layer, to a second surface of a second substrate on which a second pad is provided, a position of the first substrate and a position of the second substrate being aligned with each other based on the plurality of first mark portions and a second mark portion of the second substrate, the plurality of first mark portions and the second mark portion being electrically isolated from the plurality of memory units and a circuit of the second substrate.