US 11,942,454 B2
Package and manufacturing method thereof
Hsien-Wei Chen, Hsinchu (TW); Jie Chen, New Taipei (TW); and Ming-Fa Chen, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 9, 2022, as Appl. No. 17/739,198.
Application 17/739,198 is a continuation of application No. 16/801,156, filed on Feb. 26, 2020, granted, now 11,362,065.
Prior Publication US 2022/0262771 A1, Aug. 18, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 25/00 (2006.01); H01L 49/02 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/56 (2013.01); H01L 23/3128 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/19 (2013.01); H01L 24/24 (2013.01); H01L 24/89 (2013.01); H01L 25/50 (2013.01); H01L 28/60 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/24145 (2013.01); H01L 2224/80001 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/19041 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package, comprising:
a first die having a first interconnection structure, wherein the first interconnection structure comprises a first capacitor embedded therein;
a second die having a second interconnection structure, wherein the second interconnection structure comprises a second capacitor embedded therein, the first interconnection structure faces the second interconnection structure, the second die is stacked on the first die, and the first capacitor is electrically connected to the second capacitor; and
an encapsulant laterally encapsulating the second die.