US 11,942,447 B2
Storage layers for wafer bonding
De-Yang Chiou, Hsinchu (TW); Fu-Ting Yen, Hsinchu (TW); Yu-Yun Peng, Hsinchu (TW); and Keng-Chu Lin, Ping-Tung (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by TAIWAN SEMINCONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Aug. 27, 2021, as Appl. No. 17/459,496.
Prior Publication US 2023/0062412 A1, Mar. 2, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/32 (2013.01) [H01L 23/481 (2013.01); H01L 24/29 (2013.01); H01L 24/83 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/29188 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/83013 (2013.01); H01L 2224/83896 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/05442 (2013.01); H01L 2924/3512 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first device structure comprising at least one first device and a first storage layer, wherein the first storage layer comprises a porous material containing carbon;
a second device structure comprising at least one second device and a second storage layer, wherein the second storage layer comprises the porous material; and
a bonding layer interposed between the first and second device structures and in contact with the first and second storage layers.