US 11,942,436 B2
Passivation scheme design for wafer singulation
Hsien-Wei Chen, Hsinchu (TW); Ying-Ju Chen, Tuku Township (TW); and Ming-Fa Chen, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 9, 2022, as Appl. No. 17/883,932.
Application 17/883,932 is a division of application No. 17/006,365, filed on Aug. 28, 2020, granted, now 11,699,663.
Claims priority of provisional application 63/015,780, filed on Apr. 27, 2020.
Prior Publication US 2022/0384261 A1, Dec. 1, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 21/74 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/525 (2006.01); H01L 23/544 (2006.01); H01L 23/58 (2006.01)
CPC H01L 23/544 (2013.01) [H01L 21/74 (2013.01); H01L 21/78 (2013.01); H01L 23/3171 (2013.01); H01L 23/525 (2013.01); H01L 23/562 (2013.01); H01L 23/585 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
electrical components in the substrate;
an interconnect structure over the substrate and electrically coupled to the electrical components;
a seal ring around the interconnect structure;
a first passivation layer over the interconnect structure and the seal ring;
a dielectric layer over the first passivation layer, wherein there is a first lateral distance between a first sidewall of the first passivation layer closest to the seal ring and a sidewall of the dielectric layer closest to the seal ring; and
a second passivation layer between the first passivation layer and the interconnect structure, wherein there is a second lateral distance between a second sidewall of the second passivation layer closest to the seal ring and the sidewall of the dielectric layer closest to the seal ring, wherein the first passivation layer extends along an upper surface of the second passivation layer distal from the substrate, and along the second sidewall of the second passivation layer.