US 11,942,409 B2
High density low power interconnect using 3D die stacking
Ferran Martorell, Barcelona (ES); and Prasad Subramaniam, Stirling, NJ (US)
Assigned to MARVELL ASIA PTE LTD, Singapore (SG)
Filed by MARVELL ASIA PTE, LTD., Singapore (SG)
Filed on Jan. 24, 2022, as Appl. No. 17/582,380.
Application 17/582,380 is a continuation of application No. 16/748,633, filed on Jan. 21, 2020, granted, now 11,233,002.
Claims priority of provisional application 62/914,241, filed on Oct. 11, 2019.
Claims priority of provisional application 62/913,322, filed on Oct. 10, 2019.
Prior Publication US 2022/0148957 A1, May 12, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/48 (2006.01); H01L 21/304 (2006.01); H01L 21/66 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01); H01L 23/528 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/49838 (2013.01) [H01L 21/3043 (2013.01); H01L 21/768 (2013.01); H01L 22/34 (2013.01); H01L 23/528 (2013.01); H01L 25/0655 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first set of dies, each die comprising circuitry; and
a second set of interposer dies, the second set of interposer dies collectively having a smaller perimeter than a collective perimeter of the first set of dies, at least two dies of the first set of dies being connected to each other via at least one of the interposer dies, the at least one of the interposer dies including first connections connected to a first die of the first set of dies, second connections connected to a second die of the first set of dies, and buffers connected between the first connections and the second connections, the buffers being configured to condition signals between the first die and the second die.