US 11,942,407 B2
Semiconductor chip packages having bond over active circuit (BOAC) structures
Jeffrey Salvacion Solas, Angeles (PH); and Maricel Fabia Escaño, Angeles (PH)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Aug. 31, 2021, as Appl. No. 17/463,077.
Prior Publication US 2023/0068086 A1, Mar. 2, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/49827 (2013.01) [H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method, comprising:
forming an insulating member over a circuit on a device side of a semiconductor die;
removing a portion of the insulating member to produce a cavity;
forming a seed layer on the insulating member and within the cavity;
forming a conductive member on the seed layer in the cavity, wherein the conductive member comprises a plurality of layers of different metal materials; and
removing the seed layer from atop the insulating member, outside the cavity, after forming the conductive member in the cavity such that a remaining portion of the seed layer is positioned between the conductive member and the insulating member, wherein the seed layer abuts an outer perimeter of the conductive member.