US 11,942,403 B2
Integrated circuit package and method
Chih-Chien Pan, Taipei (TW); Li-Hui Cheng, New Taipei (TW); Chin-Fu Kao, Taipei (TW); and Szu-Wei Lu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 4, 2022, as Appl. No. 17/980,914.
Application 17/980,914 is a continuation of application No. 17/244,598, filed on Apr. 29, 2021, granted, now 11,495,526.
Application 17/244,598 is a continuation of application No. 16/707,908, filed on Dec. 9, 2019, granted, now 11,205,612, issued on Dec. 21, 2021.
Application 16/707,908 is a continuation of application No. 16/138,099, filed on Sep. 21, 2018, granted, now 10,504,824, issued on Dec. 10, 2019.
Prior Publication US 2023/0052821 A1, Feb. 16, 2023
Int. Cl. H01L 23/498 (2006.01); H01L 21/304 (2006.01); H01L 21/306 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/49811 (2013.01) [H01L 21/304 (2013.01); H01L 21/30604 (2013.01); H01L 21/561 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/49827 (2013.01); H01L 24/09 (2013.01); H01L 24/81 (2013.01); H01L 24/97 (2013.01); H01L 25/0652 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package comprising:
metal interconnects disposed over a substrate;
a first integrated circuit device attached to the metal interconnects, the first integrated circuit device having a first edge and a second edge opposite the first edge;
an underfill having a first portion disposed beneath the first integrated circuit device and having a first fillet extending along the first edge of the first integrated circuit device, an edge of the first portion of the underfill being planar with the second edge of the first integrated circuit device; and
an encapsulant around the first integrated circuit device and the underfill, the encapsulant having a first surface planar with the edge of the first portion of the underfill and the second edge of the first integrated circuit device.