US 11,942,402 B2
Laminate stacked on die for high voltage isolation capacitor
Thomas Dyer Bonifield, Dallas, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Feb. 23, 2022, as Appl. No. 17/679,065.
Application 17/679,065 is a continuation of application No. 16/806,362, filed on Mar. 2, 2020, granted, now 11,270,930.
Prior Publication US 2022/0181240 A1, Jun. 9, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/64 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01); H01L 49/02 (2006.01)
CPC H01L 23/49811 (2013.01) [H01L 21/4853 (2013.01); H01L 23/642 (2013.01); H01L 24/45 (2013.01); H01L 24/85 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 28/40 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An isolator device, comprising:
a laminate die comprising a dielectric laminate material with a metal laminate layer on one side of the dielectric laminate material, the metal laminate layer providing at least a first plate;
an integrated circuit (IC) comprising a substrate having a semiconductor surface including circuitry, the IC including a top metal layer providing at least a second plate coupled to a node in the circuitry, with at least one passivation layer on the top metal layer, and
a non-conductive die attach (NCDA) material for attaching a side of the dielectric laminate material opposite the metal laminate layer to the IC so that the first plate is at least partially over the second plate to provide a capacitor.