US 11,942,387 B2
Plated walls defining mold compound cavities
John Carlo Cruz Molina, Limay (PH); Julian Carlo Concepcion Barbadillo, Mabalacat (PH); and Ray Fredric Solis De Asis, Mabalacat (PH)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Sep. 30, 2021, as Appl. No. 17/491,354.
Prior Publication US 2023/0095185 A1, Mar. 30, 2023
Int. Cl. H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/10 (2006.01)
CPC H01L 23/315 (2013.01) [H01L 21/565 (2013.01); H01L 23/3114 (2013.01); H01L 24/16 (2013.01); H01L 25/10 (2013.01); H01L 25/50 (2013.01); H01L 2224/16145 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a wafer chip scale package (WCSP) having a circuitry formed in a device side and an insulative layer above the device side;
a wall extending vertically to form a defined space, the wall configured to prevent mold compound from flowing into the defined space;
a mold compound abutting surfaces of the wall opposing the defined space; and
a conductive terminal coupled to the circuitry and extending from the WCSP into the defined space.