US 11,942,376 B2
Method for manufacturing semiconductor structure
Chun Hsiung Tsai, Hsinchu County (TW); Cheng-Yi Peng, Taipei (TW); Ching-Hua Lee, Hsinchu (TW); Chung-Cheng Wu, Hsin-Chu County (TW); and Clement Hsingjen Wann, Carmel, NY (US)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Aug. 8, 2022, as Appl. No. 17/818,120.
Application 17/818,120 is a continuation of application No. 16/404,540, filed on May 6, 2019, granted, now 11,450,571.
Claims priority of provisional application 62/737,384, filed on Sep. 27, 2018.
Prior Publication US 2022/0384275 A1, Dec. 1, 2022
Int. Cl. H01L 21/8238 (2006.01); H01L 21/265 (2006.01); H01L 21/268 (2006.01); H01L 21/285 (2006.01); H01L 21/324 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/823821 (2013.01) [H01L 21/265 (2013.01); H01L 21/324 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01); H01L 21/823871 (2013.01); H01L 27/0924 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/26506 (2013.01); H01L 21/268 (2013.01); H01L 21/28518 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor structure, comprising:
receiving a substrate including a first conductive region and a first gate structure of a first transistor and a second conductive region and a second gate structure of a second transistor, wherein the first transistor and the second transistor have different conductive types;
consuming a thickness of a first spacer on a vertical surface of the first gate structure and a thickness of a second spacer on a vertical surface of the second gate structure;
forming a liner layer over the first spacer and the second spacer;
performing an amorphization on the first conductive region and the second conductive region concurrently by a first implantation;
performing a second implantation to introduce a P-type dopant on the first conductive region;
forming a contact material layer over the first conductive region and the second conductive region, wherein the first conductive region is implanted by the first implantation and the second implantation prior to the formation of the contact material layer, and the second conductive region is implanted by the first implantation prior to the formation of the contact material layer;
performing a thermal anneal on the first conductive region and the second conductive region; and
performing a laser anneal on the first conductive region and the second conductive region.