US 11,942,375 B2
Structure and formation method of semiconductor device with fin structures
Hsing-Hui Hsu, Hsinchu (TW); Po-Nien Chen, Miaoli County (TW); Yi-Hsuan Chung, Hsinchu (TW); Bo-Shiuan Shie, Hsinchu (TW); and Chih-Yung Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Aug. 17, 2021, as Appl. No. 17/404,443.
Application 17/404,443 is a continuation of application No. 16/526,692, filed on Jul. 30, 2019, granted, now 11,094,597.
Claims priority of provisional application 62/738,098, filed on Sep. 28, 2018.
Prior Publication US 2021/0375697 A1, Dec. 2, 2021
Int. Cl. H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/823821 (2013.01) [H01L 21/02532 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823842 (2013.01); H01L 21/823871 (2013.01); H01L 27/0924 (2013.01); H01L 27/0928 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/823892 (2013.01); H01L 29/7848 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating a complementary metal-oxide-semiconductor (CMOS) transistor, the method comprising:
forming a p-type silicon layer over a first region of a substrate;
forming an n-type silicon germanium layer over a second region of the substrate;
simultaneously etching the p-type silicon layer to have a first width and the n-type silicon germanium layer to have a second width that is less than the first width, wherein the etched p-type silicon layer having the first width is a p-type silicon fin and the etched n-type silicon germanium layer having the second width is an n-type silicon germanium fin, wherein:
an n-type single-fin transistor of the CMOS transistor includes the p-type silicon fin and a p-type single-fin transistor of the CMOS transistor includes the n-type silicon germanium fin, and
the p-type silicon layer and the n-type silicon germanium layer are simultaneously etched to have an etched width difference between the first width and the second width that is 0.5 nm to 3 nm and an etched width ratio of the first width to the second width that is 1.1 to 1.3;
forming a gate that wraps a channel portion of the p-type silicon fin and a channel portion of the n-type silicon germanium fin, wherein the gate is shared by the n-type single-fin transistor and the p-type single-fin transistor;
recessing source/drain portions of the p-type silicon fin and recessing source/drain portions of the n-type silicon germanium fin; and
forming n-type epitaxial source/drain structures on the recessed source/drain portions of the p-type silicon fin and p-type epitaxial source/drain structures on the recessed source/drain portions of the n-type silicon germanium fin, wherein the n-type single-fin transistor includes the n-type epitaxial source/drain structures and the p-type single-fin transistor includes the p-type epitaxial source/drain structures.