US 11,942,368 B2
Through silicon vias and methods of fabricating thereof
Min-Feng Kao, Chiayi (TW); Hsing-Chih Lin, Tainan (TW); Jen-Cheng Liu, Hsin-Chu (TW); and Dun-Nian Yaung, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Sep. 2, 2021, as Appl. No. 17/465,232.
Claims priority of provisional application 63/200,275, filed on Feb. 26, 2021.
Prior Publication US 2022/0277998 A1, Sep. 1, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 23/48 (2006.01)
CPC H01L 21/76898 (2013.01) [H01L 23/481 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A method comprising:
providing a semiconductor substrate having a semiconductor device disposed over the semiconductor substrate;
depositing a first dielectric layer over the semiconductor device;
forming, within the first dielectric layer, a first via, a first metal line over the first via, a first metal ring coplanar with the first via, and a second metal ring coplanar with the first metal line and on the first metal ring;
depositing a second dielectric layer over the first metal line;
forming, within the second dielectric layer, a second via, a second metal line over the second via, a third metal ring coplanar with the second via and on the second metal ring, and a fourth metal ring coplanar with the second metal line and on the third metal ring; and
forming another via through a portion of the semiconductor substrate, wherein the forming the another via includes etching the first dielectric layer and the second dielectric layer to form an opening extending through a center region of each of the first metal ring, the second metal ring, the third metal ring, and the fourth metal ring, wherein at least one of the first metal ring, the second metal ring, the third metal ring, and the fourth metal ring are laterally etched during the etching to form the opening.