US 11,942,364 B2
Selective deposition of a protective layer to reduce interconnect structure critical dimensions
Hsi-Wen Tien, Xinfeng Township (TW); Chung-Ju Lee, Hsinchu (TW); Chih Wei Lu, Hsinchu (TW); Hsin-Chieh Yao, Hsinchu (TW); Yu-Teng Dai, New Taipei (TW); and Wei-Hao Liao, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 20, 2022, as Appl. No. 17/868,845.
Application 17/868,845 is a division of application No. 17/012,427, filed on Sep. 4, 2020, granted, now 11,521,896.
Claims priority of provisional application 62/951,147, filed on Dec. 20, 2019.
Prior Publication US 2022/0352017 A1, Nov. 3, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 23/522 (2006.01); H01L 27/092 (2006.01)
CPC H01L 21/76831 (2013.01) [H01L 21/76813 (2013.01); H01L 23/5226 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/7684 (2013.01); H01L 27/092 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming an interconnect, comprising:
forming an etch stop layer (ESL) over a lower conductive structure;
forming one or more dielectric layers over the ESL;
performing a first patterning process on the one or more dielectric layers to form interconnect opening;
performing a second patterning process on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL;
selectively forming a protective layer on sidewalls of the one or more dielectric layers forming the interconnect opening;
performing a third patterning process to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure; and
forming a conductive material within the interconnect opening.