US 11,942,359 B2
Reduced semiconductor wafer bow and warpage
Abbas Ali, Plano, TX (US); Christopher Scott Whitesell, Garland, TX (US); Brian K. Kirkpatrick, Allen, TX (US); and Byron Joseph Palla, Murphy, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, P.O. Box 655474, M/S 3999 Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Nov. 30, 2021, as Appl. No. 17/538,372.
Prior Publication US 2023/0170248 A1, Jun. 1, 2023
Int. Cl. H01L 21/762 (2006.01); H01L 27/02 (2006.01); H01L 29/06 (2006.01)
CPC H01L 21/76224 (2013.01) [H01L 21/76202 (2013.01); H01L 27/0203 (2013.01); H01L 29/0649 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method of forming an integrated circuit, comprising:
concurrently forming a first front end of line (FEOL) layer at a frontside of a semiconductor substrate and a second FEOL layer at a backside of the semiconductor substrate opposite the frontside, wherein the first and second FEOL layers include a same material, and wherein the second FEOL layer has a first thickness; and
removing at least a portion of the second FEOL layer such that the second FEOL layer has a second thickness less than the first thickness as a result of removing at least the portion of the second FEOL layer.