US 11,942,185 B2
Memory device and method
Je-Min Hung, Kaohsiung (TW); Win-San Khwa, Taipei (TW); and Meng-Fan Chang, Taichung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 3, 2022, as Appl. No. 17/832,261.
Claims priority of provisional application 63/281,908, filed on Nov. 22, 2021.
Prior Publication US 2023/0162769 A1, May 25, 2023
Int. Cl. G11C 7/12 (2006.01); G06F 7/544 (2006.01); G11C 7/10 (2006.01); G11C 7/14 (2006.01); G11C 7/16 (2006.01); G11C 7/22 (2006.01)
CPC G11C 7/222 (2013.01) [G06F 7/5443 (2013.01); G11C 7/1063 (2013.01); G11C 7/109 (2013.01); G11C 7/12 (2013.01); G11C 7/14 (2013.01); G11C 7/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An Input/Output (I/O) circuit for a memory device, wherein the I/O circuit comprises:
a charge integration circuit coupled to a bitline of the memory device, wherein the charge integration circuit provides a sensing voltage based on a decrease of a voltage on the bitline;
a comparator coupled to the charge integration circuit, wherein the comparator compares the sensing voltage with a reference voltage and provides an output voltage based on the comparison; and
a time-to-digital converter coupled to the comparator, wherein the time-to-digital convertor converts a time associated with the output voltage to a digital value.