US 11,942,182 B2
Memory and system supporting parallel and serial access modes
Scott C. Best, Palo Alto, CA (US); Frederick A. Ware, Los Altos Hills, CA (US); and William N. Ng, San Francisco, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Dec. 28, 2022, as Appl. No. 18/089,668.
Application 18/089,668 is a continuation of application No. 17/328,211, filed on May 24, 2021, granted, now 11,562,778.
Application 17/328,211 is a continuation of application No. 15/721,755, filed on Sep. 30, 2017, granted, now 11,049,532, issued on Jun. 29, 2021.
Application 15/721,755 is a continuation of application No. 14/737,147, filed on Jun. 11, 2015, granted, now 9,792,965, issued on Oct. 17, 2017.
Claims priority of provisional application 62/013,312, filed on Jun. 17, 2014.
Prior Publication US 2023/0238041 A1, Jul. 27, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/10 (2006.01); G11C 5/04 (2006.01)
CPC G11C 7/1093 (2013.01) [G11C 5/04 (2013.01); G11C 7/1003 (2013.01); G11C 7/1066 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An integrated buffer circuit for buffering signals on a first memory to and from an integrated controller circuit, the integrated buffer circuit comprising:
a first timing port to receive a timing signal from the integrated controller circuit;
a second timing port to transmit the timing signal received on the first timing port to a second memory;
a third timing port to receive the timing signal transmitted from the second timing port back from the second memory;
a first read port to receive first read signals from the second memory timed to the timing signal on the third timing port;
a fourth timing port to transmit the timing signal received on the third timing port to the integrated controller circuit;
a bidirectional port to receive second read signals from the first memory; and
a second read port to transmit the first read signals and the second read signals to the integrated controller circuit and timed to the timing signal on the fourth timing port.