US 11,942,178 B2
Sense amplifier circuit and method
Jui-Jen Wu, Hsinchu (TW); Win-San Khwa, Hsinchu (TW); Jen-Chieh Liu, Hsinchu (TW); and Meng-Fan Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Feb. 18, 2022, as Appl. No. 17/675,901.
Prior Publication US 2023/0267970 A1, Aug. 24, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 7/06 (2006.01); G11C 7/08 (2006.01)
CPC G11C 7/065 (2013.01) [G11C 7/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
a reference voltage node;
first and second data lines;
a sense amplifier comprising first and second input terminals;
a first switching device coupled between the first data line and the first input terminal;
a second switching device coupled between the second data line and the second input terminal;
a third switching device coupled between the first data line and a first node;
a fourth switching device coupled between the second data line and a second node;
a fifth switching device coupled between the first node and the reference voltage node;
a sixth switching device coupled between the second node and the reference voltage node;
a first capacitive device coupled between the first node and the second input terminal; and
a second capacitive device coupled between the second node and the first input terminal,
wherein the circuit is configured to
in a first operational mode, switch on each of the first through fourth switching devices and switch off each of the fifth and sixth switching devices, and
in a second operational mode, switch off each of the first through fourth switching devices and switch on each of the fifth and sixth switching devices.