US 11,942,177 B2
Using embedded switches for reducing capacitive loading on a memory system
Chia-Ta Yu, Hsinchu (TW); Chia-En Huang, Xinfeng Township (TW); Sai-Hooi Yeong, Zhubei (TW); Yih Wang, Hsinchu (TW); and Yi-Ching Liu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 10, 2022, as Appl. No. 17/572,370.
Application 17/572,370 is a continuation of application No. 17/103,767, filed on Nov. 24, 2020, granted, now 11,238,904.
Prior Publication US 2022/0165312 A1, May 26, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/02 (2006.01); G11C 7/12 (2006.01); G11C 7/18 (2006.01); G11C 8/08 (2006.01); G11C 8/14 (2006.01)
CPC G11C 7/02 (2013.01) [G11C 7/12 (2013.01); G11C 7/18 (2013.01); G11C 8/08 (2013.01); G11C 8/14 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory array comprising:
a set of first memory cells coupled in parallel between a first local select line and a first local bit line;
a set of second memory cells coupled in parallel between a second local select line and a second local bit line;
a set of first switches coupled to a global bit line;
a set of second switches coupled between the first local bit line and the first switches; and
a set of third switches coupled between the second local bit line and the first switches.