US 11,942,175 B2
Memory device protection using interleaved multibit symbols
Paolo Amato, Treviglio (IT); Marco Sforzin, Cernusco Sul Naviglio (IT); and Stephen S. Pawlowski, Beaverton, OR (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 27, 2022, as Appl. No. 17/874,897.
Application 17/874,897 is a continuation of application No. 17/124,197, filed on Dec. 16, 2020, granted, now 11,404,136.
Prior Publication US 2022/0359034 A1, Nov. 10, 2022
Int. Cl. G11C 29/42 (2006.01); G11C 7/10 (2006.01); G11C 29/10 (2006.01); G11C 29/44 (2006.01); H03M 13/27 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 7/1042 (2013.01); G11C 29/10 (2013.01); G11C 29/44 (2013.01); H03M 13/27 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of memory devices; and
a controller coupled to the plurality of memory devices via a plurality of respective channels, the controller configured to:
read, from the plurality of memory devices and during one or more data bursts, a number of codewords each comprising a number of multibit user data symbols respectively corresponding to different memory devices of the plurality of memory devices; and
correct an error of one or more multibit symbols of at least one codeword of the number codewords and corresponding to one or more memory devices of the plurality of memory devices.