CPC G11C 29/42 (2013.01) [G11C 7/04 (2013.01); G11C 29/1201 (2013.01); G11C 29/4401 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01)] | 23 Claims |
1. A memory system, comprising:
one or more memory devices comprising a block of memory cells; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
determine a first quantity of access errors for a first subblock of the block of memory cells;
determine a second quantity of access errors for a second subblock of the block of memory cells; and
retire the block of memory cells based at least in part on a difference between the first quantity of access errors and the second quantity of access errors satisfying a threshold.
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