US 11,942,174 B2
Topology-based retirement in a memory system
Chun S. Yeung, San Jose, CA (US); Deping He, Boise, ID (US); and Jonathan S. Parry, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 12, 2022, as Appl. No. 17/574,024.
Claims priority of provisional application 63/147,679, filed on Feb. 9, 2021.
Prior Publication US 2022/0254434 A1, Aug. 11, 2022
Int. Cl. G11C 29/42 (2006.01); G11C 7/04 (2006.01); G11C 29/12 (2006.01); G11C 29/44 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 7/04 (2013.01); G11C 29/1201 (2013.01); G11C 29/4401 (2013.01); G11C 2029/1202 (2013.01); G11C 2029/1204 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory devices comprising a block of memory cells; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
determine a first quantity of access errors for a first subblock of the block of memory cells;
determine a second quantity of access errors for a second subblock of the block of memory cells; and
retire the block of memory cells based at least in part on a difference between the first quantity of access errors and the second quantity of access errors satisfying a threshold.