	US 11,942,169 B2
	Semiconductor memory structure
Hsin-Wen Su, Hsinchu (TW); Kian-Long Lim, Hsinchu (TW); Wen-Chun Keng, Hsinchu County (TW); Chang-Ta Yang, Hsinchu (TW); and Shih-Hao Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 20, 2022, as Appl. No. 17/813,891.
Application 17/813,891 is a continuation of application No. 16/837,227, filed on Apr. 1, 2020, granted, now 11,462,282.
Prior Publication US 2022/0359026 A1, Nov. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 17/18 (2006.01); G11C 7/18 (2006.01); H10B 20/00 (2023.01)

CPC G11C 17/18 (2013.01) [G11C 7/18 (2013.01); H10B 20/00 (2023.02)]

20 Claims

1. A semiconductor device, comprising:

a first conductive via that electrically couples a first metal line to a first gate structure in a first active region, wherein the first conductive via is disposed over the first active region; and

a second metal line parallel to the first metal line and electrically coupled to a source/drain region of the first active region by a second conductive via;

wherein the first and second metal lines are formed within a same interconnect layer; and

wherein the first active region is associated with a first memory cell including a first program word line, a second program word line, a first read word line, and a second read word line.